1. Field of the Invention
The embodiments discussed herein relate to an operational amplifier circuit.
2. Background of the Related Art
Operational amplifiers are utilized as analog signal amplifiers or digital signal comparators, and a two stage configuration including an input stage of a differential amplifier circuit and an output stage of a common source circuit is widely known (for example, refer to Hirokazu Yoshizawa, “CMOS OP Amplifier Circuit, Basics of Practical Design”, the first edition, CQ Publishing Co., Ltd., May 15, 2007, pp. 137-139).
FIG. 6 is a circuit diagram illustrating an example of a basic two-stage operational amplifier circuit. FIG. 7 is a circuit diagram illustrating a configuration of a voltage follower utilizing the operational amplifier circuit. FIG. 8 illustrates an example of input-output characteristics of the voltage follower.
The basic operational amplifier circuit includes P channel MOSFETs (hereinafter, referred to as PMOS transistor) M1, M2, and M3 and N channel MOSFETs (hereinafter, referred to as NMOS transistor) M4 and M5, as an input stage, as illustrated in FIG. 6. Also, the operational amplifier circuit includes a PMOS transistor M6 and an NMOS transistor M7 as an output stage.
A PMOS differential pair including the PMOS transistors M2 and M3 amplifies the difference between common-mode input voltages that are applied to a pair of input terminals IN+ and IN−. A predetermined constant voltage is applied on a bias terminal Bias, so that the PMOS transistor M1 provides an electric current source for the PMOS differential pair. A current mirror circuit including the NMOS transistors M4 and M5 is an active load of the PMOS differential pair. A connection point between the PMOS transistor M3 and the NMOS transistor M5 is connected to the NMOS transistor M7 of the output stage. A connection point between the NMOS transistor M7 and the PMOS transistor M6 that provides an electric current source for the NMOS transistor M7 is connected to an output terminal Vout. Also, in this operational amplifier circuit, a series circuit consisting of a phase compensation capacitor C1 and a resistance R1 is connected to the gate and the drain of the NMOS transistor M7.
The operation of the operational amplifier circuit of the above configuration, which is utilized as a voltage follower, will be described. As illustrated in FIG. 7, the voltage follower is a non-inverting amplifier circuit whose amplification rate is 1, and its input terminal Vin corresponds to the input terminal IN+ illustrated in FIG. 6, and its output terminal Vout is connected to the input terminal IN− illustrated in FIG. 6.
Here, a rectangular wave signal is assumed to be input into the voltage follower. The PMOS transistor M3 of the PMOS differential pair is turned off, when a high level voltage of a rectangular wave (for example, a voltage close to the power supply voltage VDD) is input into the input terminal Vin. Thereby, the ground potential (0V) is applied to the gate of the NMOS transistor M7 of the output stage, in order to turn off the NMOS transistor M7, and the voltage close to the power supply voltage VDD is output to the output terminal Vout via the PMOS transistor M6, as illustrated in FIG. 8.
Next, a situation in which a falling edge signal of a rectangular wave (for example, a voltage that drops to the ground potential) is input into the input terminal Vin will be described (for example, refer to Hirokazu Yoshizawa, “CMOS OP Amplifier Circuit, Basics of Practical Design”, the first edition, CQ Publishing Co., Ltd., May 15, 2007, pp. 137-139, FIGS. 7-39). When a falling edge signal of a rectangular wave is input, the PMOS transistor M3 of the PMOS differential pair turns on immediately. In this case, all electric current flowing in the PMOS transistor M1 flows into the PMOS transistors M3. On the other hand, electric current does not flow in the PMOS transistor M2 of the PMOS differential pair, and therefore electric current does not flow in the NMOS transistor M4 and in the NMOS transistor M5 having a common gate with the NMOS transistor M4. Thus, all electric current flowing in the PMOS transistor M3 flows into the capacitor C1 in order to charge the capacitor C1. Simultaneously, the NMOS transistor M7 is turned on by a rise of the gate voltage of the NMOS transistor M7, and the voltage of the output terminal Vout starts falling as illustrated in FIG. 8.
The voltage of the output terminal Vout falls as the capacitor C1 is charged, and the voltage of the output terminal Vout becomes equal to the voltage of the input terminal Vin, when the gate voltages of the PMOS transistors M2 and M3 become equal. Thereby, equal amounts of electric currents flow in the PMOS transistors M2 and M3, and equal amounts of electric currents flow in the NMOS transistors M4 and M5 of the current mirror circuit as well. As the equal amounts of the electric currents flow in the PMOS transistor M3 and the NMOS transistor M5, the capacitor C1 is fully charged.
As described above, when the falling edge signal of the rectangular wave is input into the input terminal Vin of the voltage follower, the capacitor C1 is charged by a bias current that flows in the PMOS transistor M1, and the voltage of the output terminal Vout falls. The charge into the capacitor C1 is completed, when the voltage of the output terminal Vout falls to the ground potential. In this case, a slew rate, i.e., a value obtained by dividing the voltage of the output terminal Vout by the time taken for the voltage of the output terminal Vout to fall, is dependent on the capacitance value of the capacitor C1 and the current value for charging the capacitor C1.
Here, the time taken for the voltage of the output terminal Vout to fall is to be shortened in order to make a high-speed operational amplifier circuit of a high slew rate at a falling edge of a rectangular wave. The capacitance value of the capacitor C1 may be reduced, or the current value for charging the capacitor C1 may be increased, in order to shorten the time taken for the voltage of the output terminal Vout to fall, and to make the slope of the falling edge steeper.
However, the capacitance value of the phase compensation capacitor depends on the condition of phase compensation, and therefore it is difficult to make a small change in order to improve the slew rate. On the other hand, as the current value for charging the capacitor increases, the current value of the electric current source that supplies electric current to the differential pair of the input stage increases, and accordingly the bias current increases. Such increase of the bias current is very disadvantageous for an operational amplifier circuit employed in a mobile device, which preferably consumes less electric power, particularly.